Phase lock loops are used to generate a set of output frequencies that are accurately controlled by a reference frequency. The frequency step sizes are controlled by a reference frequency divided by R. The output frequency is N times the step size. For many applications, a Tri-State phase detector is the method of choice of implementing a phase lock loop (PLL). One advantage of Tri-State phase detectors over Sample-and-Hold phase detectors or phase lock loops is in low power applications.
FIG. 1 is a prior art block diagram that illustrates a standard non-adaptive phase lock loop implementation. The phase lock loop is driven by an accurate frequency source, such as a crystal oscillator 22. Note that other types of accurate frequency sources are well known in the art. The output of the frequency source 22 is the oscillator frequency 23. The oscillator frequency 23 is divided by a first frequency divider 24. This first frequency divider 24 divides by an integer "R". The R frequency divider 24 sets the step size or reference frequency 25.
A voltage control oscillator (VCO) 30 generates an output frequency 36. The output frequency 36 is divided by integer "N" by the N frequency divider 32. The output of the N frequency divider 32 is equal to the reference frequency 25 which is the output of the R frequency divider 24. Phase detector (PD) 26 compares the outputs of the R frequency divider 24 and the N frequency divider 32. The phase detector 26 generates output current pulses proportional to the error between divider signals 25 and 34. These error pulses from the phase detector 26 are received as input by a charge pump 28. The charge pump 28 produces current sinking or sourcing current pulses ultimately for a loop filter 38 which is applied to voltage control oscillator (VCO) 30.
A typical loop filter 38 is shown. It consists of loop filter capacitor 40 in series with loop damping resistor 42. In parallel with loop filter capacitor 40 and loop damping resistor 42 is first pole capacitor 44. This is the first pole of the loop filter. The second pole of the loop filter consists of second pole resistor 46 and second pole capacitor 48.
The bandwidth of the PLL is calculated by F.sub.u =K.sub.0 *I*R/2*.PI.*N where K.sub.0, is the VCO 30 tuning sensitivity in Hertz/volts, I is the current pulse amplitude in amperes, R is the value of loop damping resistor 42 in Ohms. Capacitors 40, 44, 48 and resistor 46 are selected for desired loop dynamics. Values of components of the loop filter along with current I, K.sub.0, and N determine response time to change in frequency and of the sampling frequency 25, 34 from the charge pump 28. A compromise exists between fast response time to changes in frequency and adequate suppression of spurious outputs from VCO 30.
FIG. 2 is a prior art block diagram of an improved phase lock loop shown in FIG. 1. It is currently implemented by National Semiconductor in their phase lock loop products, and henceforth is known as the "National" solution. The primary difference between the National solution in FIG. 2 and the prior art solution illustrated in FIG. 1 is in the loop filter 38. The National solution has an extra gating input to the loop filter 38. Charge pump 28 generates one of two currents 58. In the example illustrated in FIG. 2, the one current is four times the other current. In the high current mode, connection 59 of the loop filter 38 is connected to ground. At the same time that the current is increased by a factor of 4, the N divider 32 and the R divider 24 are each reduced by a factor of 4. The reason that this division or reduction is done is that by increasing the current by a factor of 4, reducing the two dividers 24, 32 by 4 and by reducing the damping resistor R 42 by 4, the result is a loop bandwidth that is 4 times greater than the original. The purpose of this increase in loop bandwidth is to make the response faster to a change in frequency. Note that loop filter capacitor 40 is replaced by loop capacitor filter 50, and loop damping resistor 42 is replaced by a first loop damping resistor 52 and a second loop damping resistor 54 in FIG. 2. In high current mode, the second or lower loop damping resistor 54 is shorted out of the circuit. First pole of the loop filter 44 is replaced by a comparable capacitor 56 in the National solution. Note however that the second pole of loop filter 38 consisting of resistor 46 and capacitor 48 has been removed. The reason for this removal is to not deteriorate loop stability in the high current mode.
The intent of this National solution approach is to allow a phase lock loop (PLL) to more quickly to adjust to a new output frequency. However, since the step size is four times larger than ultimately desired, a worse case frequency error can occur which is two times the desired channel spacing. As a result, the PLL locks quickly, but with the large frequency error, the time saved to arrive at a final frequency is not significantly improved. This problem is aggravated because the loop filter 38 must be slowed down to compensate for the lack of the second pole of the loop filter 38 comprising resistor 46 and capacitor 48. If the second pole of the loop filter 38 is not removed, the spurious output of the VCO 30 will often not be at an acceptable level.